package group
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import firrtl.options.TargetDirAnnotation


object u_group extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog","--emission-options=disableMemRandomization,disableRegisterRandomization"),
    Seq(ChiselGeneratorAnnotation(() => new group()),
      TargetDirAnnotation("Verilog"))
  )
}

object u_emitter extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog","--emission-options=disableMemRandomization,disableRegisterRandomization"),
    Seq(ChiselGeneratorAnnotation(() => new emitter()),
      TargetDirAnnotation("Verilog"))
  )
}

object u_transfer extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog","--emission-options=disableMemRandomization,disableRegisterRandomization"),
    Seq(ChiselGeneratorAnnotation(() => new transfer()),
      TargetDirAnnotation("Verilog"))
  )
}